Layout Generation of Matched Capacitors
نویسندگان
چکیده
In this paper we discuss layout generation of on-chip matched capacitors with accurate capacitance ratios. Capacitor sizing and placement suitable for design of error insensitive capacitance ratios are discussed including a proposed algoritm for common-centriod placement. Also, a regular layout structure is proposed that is suitable for implementation of capacitors with well matched capacitance ratios.
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